Ambiq Jobs

AI-Assisted Foundation IP Development Intern

Ambiq

AI-Assisted Foundation IP Development Intern

Posted 2 Days Ago

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In-Office

Singapore

Internship

Easy Apply

In-Office

Singapore

Internship

Supports foundation IP development for edge AI SoCs through standard-cell circuit design, simulation, layout, characterization, and debugging. Uses Python, pandas, and scikit-learn to analyze timing, power, noise, and process-voltage-temperature data, identify outliers, and build predictive models that reduce simulation effort. The intern also performs DRC/LVS cleanup, investigates simulation mismatches, and documents findings for the IP team.

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Company Overview

Ambiq is on a mission to enable intelligence everywhere — powering the AI edge revolution with the world's lowest-power semiconductor solutions.

Built on our proprietary sub- and near-threshold technology, our chips deliver multi-fold improvements in energy efficiency without costly process scaling. Since 2010, we've shipped over 300 million units to customers building smarter wearables, medical devices, IoT products, and AI-powered edge applications.

Our cross-functional teams span design, research, development, production, marketing, sales, and operations across Austin, Hsinchu, Shanghai, Shenzhen, and Singapore. We move fast, tackle hard problems, and create space for people to grow through complex, meaningful work that shapes the future of technology.

We're looking for self-motivated, creative problem-solvers who are eager to push technological limits and make a real impact in energy efficiency.

At Ambiq, we live by five values: Innovate. Collaborate. Focus. Learn. Achieve.

If that's you, join us — the intelligence everywhere revolution starts here.

AI-Assisted Foundation IP Development InternAbout the Role

Part of Foundation IP team on standard cell and memory compiler IP for edge AI SoCs — including using data analysis and ML to spot trends in characterization data and flag outliers early.

Responsibilities

Support circuit design, spice/Monte Carlo simulation and layout of standard cells
Perform layout tasks (placement, routing, DRC/LVS cleanup) for foundation IP
Characterize standard cells (timing, power, noise) across PVT corners
Run characterization flows using tools like Liberate
Analyze characterization data using Python (pandas, scikit-learn) to find trends and outliers
Build simple predictive models to flag likely failures and reduce simulation runs
Help debug mismatches between simulated and characterized results
Document findings and share with the IP team

Qualifications

Pursuing a BS in EE, CE, Microelectronics, or related field (rising Junior/Senior)
Coursework in digital logic, Analog, AI/ML, data Science, VLSI, or semiconductor devices
Basic understanding of circuit design and IC layout (DRC/LVS) concepts
Working knowledge of Python and basic ML concepts (regression, clustering)
Comfort working with large datasets

Nice to Have

Exposure to layout/schematic tools (Virtuoso, Calibre) or characterization tools (Liberate, Tempus)
A class project applying ML to engineering or scientific data
Interest in low-power IP for edge AI/IoT

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